CS501 Assignment No. 4
Wednesday, June 15, 2011 Posted In CS and IT Edit This
Assignment No. 04
Semester Spring 2011
Advance Computer Architecture - CS501
Total Marks: 15
Due Date: 19/06/2011
Objective:
Q No. 1 Marks 10
An I/O device transfers data at a rate of 5MB/s over a 100MB/s bus. The data is transferred in 2KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA.
Semester Spring 2011
Advance Computer Architecture - CS501
Total Marks: 15
Due Date: 19/06/2011
Objective:
To learn and understand basic concepts of I/O subsystems, and DMA
Instructions:
Please read the following instructions carefully before solving & submitting assignment:
Assignment should be in your own wordings not copied from net, handouts or books.
It should be clear that your assignment will not get any credit (zero marks) if:
- The assignment is submitted after due date.
- The submitted assignment does not open or file corrupt.
- The assignment is copied (from other student or copy from handouts or internet).
- Student ID is not mentioned in the assignment File or name of file is other than student ID.
Note: You have to provide solution with all the calculations and formulations involved, else no marks will be awarded.
For any query about the assignment, contact at cs501@vu.edu.pk
Q No. 1 Marks 10
An I/O device transfers data at a rate of 5MB/s over a 100MB/s bus. The data is transferred in 2KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA.
Q. No. 2 Marks 5
A 4 K byte block of data is read from a disk drive. What is the overall data transmission rate if the disk drive has a latency of 7 ms, and a burst bandwidth of 2 MB per second?
